1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for writing data in this device, and more particularly, the present invention relates to an improved technology of continuous writing operation for the nonvolatile semiconductor memory device with a virtual ground line type of a memory cell array structure.
2. Description of the Related Art
For example, the nonvolatile semiconductor memory device may include a memory cell having a diffusion bit line which is formed by an impure diffusion area and a virtual ground line type of a flush memory having a source and a drain formed by a diffusion bit line. More specifically, this nonvolatile semiconductor memory device is provided with a memory cell array, in which memory cells having a floating gate and a control gate arranged in a layer via an insulation film on a semiconductor substrate are aligned in a matrix in rows and columns. In this memory cell array, the sources or the drains of the memory cells arranged on the same column is connected by a diffusion bit line and control gates of respective memory cells are connected by a word line. Then, the diffusion bit line is connected to a bit line contact in units of predetermined continued word lines to be connected to a main bit line (a metal wire).
Writing operation and erasing operation of this nonvolatile semiconductor memory device are carried out by injecting or pulling out a charge in and from the floating gate of the memory cell. The case that the writing operation is carried out by channel hot electron injection in this nonvolatile semiconductor memory device will be described below.
The writing operation is made by applying a positive voltage to a selected word line and a selected bit line connected to the selected memory cell that is selected, respectively, for example, applying a voltage of +10V to the selected word line and a voltage of +5V to the selected bit line, respectively. As a result of this, a channel hot electron is generated and an electron is injected in the floating gate, and this increases a threshold voltage of the memory cell. In this case, the state that the threshold value of the memory cell is set to be higher than a predetermined value is defined as a writing state. In this case, writing current is supplied to the diffusion bit line, so that a voltage variation derived from a product of this writing current and a resistance value of the diffusion bit line is generated.
FIG. 5 shows the order of the writing operation of the memory cell carried out in a virtual ground line type of a conventional nonvolatile semiconductor memory device. Further, in the initial state, the all memory cells are made into an erasing state such that the threshold value is set to be lower than a predetermined value. When carrying out the writing operation, starting the writing operation sequentially from the memory cell connected to the word line at a left side of the drawing nearest to the bit line contact, the writing operation into the memory cell which is connected to the adjacent word line will be carried out toward a right side of the drawing. In other words, writing is done in the order of a row address, more specifically, in the order of row addresses WLO→WL1 . . . →WLn. Finally, the threshold voltages of the all memory cells are set to be no less than a predetermined value.
However, in the virtual ground line type of the nonvolatile semiconductor memory device in which the shortest distance from each drain of the memory cells to the bit line contact varies in accordance with the arrangement place of the memory cell in the column direction, a drain voltage drop derived from a product of the resistance of the diffusion bit line formed in the impure diffusion area and the writing current is generated.
Then, in the case of carrying out the writing operation sequentially for a plurality of memory cells on the same column while moving the selected memory cell into a certain direction, as shown in FIG. 6, in the memory cells near the bit line contact after writing is started, there are many bit line leak currents since many memory cells in the erasing state are connected to the bit line, however, the resistance value of the diffusion bit line is small and the drain voltage is lowered little because the resistance value of the diffusion bit line is small. On the other hand, in the memory cell farthest from the bit line contact, namely, in the memory cell located in the middle of two bit line contacts, the distance from the bit line contact is long, so that the resistance value of the diffusion bit line is made the largest. Further, since nearly half of the memory cells in the erasing state (the state that the threshold voltage is low) remain in the word line address that is not written, there is a bit line leak current to be generated when the threshold value of the memory cell in the erasing state is low and lowering of the drain voltage becomes the highest. Basically, the farther the memory cell is separated from the bit line contact, the lower the drain voltage becomes and the slower a writing rate becomes. In other words, there is a difference between the cells near the bit line contact and the cells far from the bit line contact, and then, the writing rates are varied in a direction of the word line.
In recent years, due to a large volume of the nonvolatile semiconductor memory device, it is general that multilevel writing is carried out; however, if the writing rates are largely varied, a divided margin between respective states upon multilevel writing is decreased, and this gives an impact on the reading operation and reliability in maintain of an electric charge.
As such a multilevel writing technology to decrease variation of the writing rates of the memory cell, there is a technology to change a voltage applied to each memory cell in accordance with the arrangement place of the memory cell upon writing (for example, refer to Japanese Application Laid-Open No. 11-066876). In this technology, by setting a higher applied voltage (a word line voltage) upon writing for the memory cell having a late writing rate as compared to the memory cell having a fast writing rate, variation of the writing rates of respective cells are decreased.